This invention relates generally to encoding of data for transmission over data communications networks.
Data to be transmitted over a communications network is commonly encoded in order to improve transmission characteristics, e.g. to improve data recovery rates and/or compress data for higher data transfer rates. In high-speed interconnect technologies such as 10 Gb/s, 40 Gb/s and 100 Gb/s Ethernet, InfiniBand, and 10-, 16- and 20-gigabit fiber channel, data is formatted in 64-bit blocks which undergo various stages of encoding and other processing prior to transmission. For example, an encoding stage employs a rate-64/66 modulation code. This code is a block code with the redundancy of two header bits per 64-bit payload. The 64-bit payload of each 66-bit block is either a control block, containing control information for the transmission process, or a data block containing actual data (i.e. user data, CRC (cyclic redundancy check) data and other “non-control” data). The 2-bit header of the 66-bit block indicates whether the attached payload is a data block or a control block. The 66-bit blocks are then subject to additional processing before transmission. For example, the payload of encoded blocks may be distributed over multiple channels, or “lanes”, for transmission over the network link after forward error correction (FEC) and insertion of alignment markers for block recovery at the receiver.
The particular format of data and control blocks is defined by the appropriate transmission protocol. In general, different types of control block are defined for use in the system, and each control block includes a dedicated field which indicates the type of that control block. This field, referred to herein as a “block-type field”, may contain one of a predefined set of K bit-patterns each corresponding to a respective one of K different types of control block used in the transmission system. In 100 Gb/s Ethernet as defined in IEEE 802.3ba-2010, for example, the block format is shown in FIG. 1 of the accompanying drawings. The left-hand column of this table indicates the eight data or control “characters” (represented by letters D, C, O, S or T with suffix 0 to 7 denoting position in the block format) of data and control blocks. The rest of the table indicates the 66-bit output block format for the rate 64/66 modulation code. The 66-bit format for data blocks is shown at the top of the table. This starts with the 2-bit header 01 indicating that the 64-bit payload is a data block. There are eleven different types of control block in this instance and the 66-bit format for these is as indicated beneath the data block format. In each case this starts with the 2-bit header 10 indicating that the 64-bit payload is a control block. The control block commences with an 8-bit block-type field. This contains a bit-pattern representing one of eleven different values, indicated in hexadecimal in the column headed “Block Type Field”, for the eleven different types of control block. The set of eleven 8-bit patterns constitute a rate-4/8 code, with Hamming distance 4, for indicating the eleven different types of control block. In control blocks containing a character denoted by S, T and O, this character is implied by the block type field. The control blocks containing the character T or O give rise to zero padding bits as indicated by vertical lines and 0x000—0000 in the figure. The hexadecimal number 0x000—0000 corresponds to the 28-bit all-zero pattern.
The transmission-side processing of blocks may include an encoding stage designed to increase data rates via compression. This encoding process is often referred to as “transcoding”. The corresponding decoding process on the receiver side is referred to herein as “inverse transcoding”. In the applications discussed above, for example, transcoding can be used to transform a group of N data or control blocks into a single output block for transmission (typically after some additional processing) over the communications link. For instance, N 66-bit blocks generated by the rate 64/66 modulation encoder may be converted into a single (N*64+L)-bit block. Note that if L<2N, this transcoding process always results in compression. Existing fixed-rate transcoding schemes of this type, reshuffle (rearrange) the order of the incoming blocks in order to achieve compression. An example is described in “FEC Proposal for NRZ-Based 100G-KR Systems”, Zhongfeng Wang, Broadcom, Feb. 8, 2012. The operation of this transcoding scheme is illustrated in FIG. 2 of the accompanying drawings. The left-hand side of this figure illustrates a sequence of N=4 66-bit blocks, consisting of two data blocks (header 01) alternating with two control blocks (header 10), where “Ca” and “Cb” represent the 8-bit block-type field of the control blocks here. The output block of the transcoding process is formatted as shown on the right-hand side of the figure. The output block consists of 257 bits commencing with a single sync bit 0 shown in the upper left corner of the block. The remainder of the block is constructed by deleting all 2-bit headers from the input blocks. All input control blocks are grouped together at the start of the output block, after the sync bit. The block-type field of each control block is replaced by an 8-bit field denoted by Ta and Tb in the figure. This field consists of a 1-bit flag F, a 3-bit position field POS, and a 4-bit code field CBT. The flag F indicates whether the next (i.e. after the current) block is a control block (F=1) or a data block (F=0). The code field CBT is a 4-bit encoding indicating the control block type. The POS field consists of a 2-bit position index which indicates the original position of the current control block in the sequence of four input blocks, and 1-bit parity information. The 1-bit parity is chosen as the parity of the 1-bit flag F, the 2-bit position index and the 4-bit CBT code. After deletion of the input block header bits, this scheme effectively applies a rate 256/257 code to the four 64-bit data and control blocks at the input. Similar transcoding schemes, based on a rate 512/513 code, have been proposed to convert eight incoming 66-bit blocks, each with 64-bit payload, into a single 513-bit transcoded block.
The above transcoding schemes incur a latency penalty corresponding to the size of the N-block sequence on both the transmitter and receiver sides due to the need to reorder data and control blocks during transcoding and inverse transcoding. For example, assuming a data rate of 25 Gb/s, the aforementioned 512 bit/513 bit transcoding of successive sequences of eight input blocks results in a latency of about 20.5 ns on both the transmitter and receiver sides. Link latency is a parameter that is of critical importance in link design. One of the requirements for 100 Gb/s transmission over backplane and copper cable currently being standardized by the IEEE 802.3bj task force is that the architecture should allow implementation of the transcoding/FEC scheme with a total latency of less than 100 ns. Reduction of latency associated with transcoding is therefore desirable.